1. Field
An embodiment of the present invention relates to the field of high frequency integrated circuits and, more particularly, to high frequency integrated circuits that include domino and, in some cases, ratio or other power contention-susceptible logic.
2. Discussion of Related Art
Advances in semiconductor manufacturing technologies have enabled circuit designers to continue to integrate more transistors on a single die. At the same time, computer architecture, and more specifically, processor architecture, continues to focus on shorter and shorter cycle times.
Domino logic is frequently used to achieve high-speed operation and to reduce die area and output capacitance as compared to static complementary metal oxide semiconductor (CMOS) logic.
As clock speeds continue to increase (and thus, cycle times continue to decrease) and/or where certain parts of a chip operate at a much higher frequency, limitations of conventional logic circuits, including conventional domino logic circuits, may prevent such circuits from operating properly at the higher clock speeds.
Further, many conventional domino logic circuits operate using a two-phase clock. For very high operating frequencies, it may not be feasible to generate and distribute a two-phase clock due to noise, clock jitter and/or other issues. Hence, a higher frequency clock may be generated locally and such clocks tend to be pulsed clocks.
Ratio logic has been used in some cases as a high-speed and area-efficient way to realize logical NOR functions, for example. Use of ratio logic in this manner can eliminate the need for P device stacks that are both large and slow. Ratio logic can typically only be used in pulsed-clock domino circuits, however, due to the fact that indefinite or very long contention may be caused when a normal two-phase clock is stopped or slowed down to a very low speed.
Thus, for some current circuit designs, a narrowly pulsed clock is used to enable use of ratio logic and achieve high-speed operation. Where a narrowly pulsed clock is used instead of a conventional two-phase clock, logic may be more susceptible to functional errors due to race conditions making such circuits more difficult for design engineers to work with. Further, such circuits often push the limits of design tool capability, can limit timing design space and increase design time due to their complexity and narrow margins.